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AI Chiplet Architectures Redefining Test Insertions
['Jeorge Hurtarte', 'Technical Paper Link', 'Tom Katsioulas', 'Alex', 'Matt Bailey', 'Alexis R. Ware', 'Yağız Boz', 'Murugavel Ganesan', 'F. Chen', 'B.S. Deepaksubramanyan']
Semiconductor Engineering
Key test factors are grounded in geometry, pitch, and interconnect density – variables that directly affect probing, access, and test coverage.
Known-good everything: The economic imperativeHigh-value AI accelerator companies change test strategies and test insertion steps based on economic drivers.
This includes mechanical scale, current delivery, power dissipation, contact integrity, probe force, and thermo-mechanical warpage stability at probe.
At this stage, electrical access is typically limited to C4 bump interfaces, requiring test to be performed before substrate attach using probe-based methods rather than traditional package test.
As a result, test access must be brought physically closer to the device under test, thus minimizing parasitics and maintaining signal fidelity.