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Optimizing Chiplet Placement And Interposer Footprint For 2.5D Systems (A*STAR)
['Technical Paper Link', 'Tom Katsioulas', 'Alex', 'Matt Bailey', 'Alexis R. Ware', 'Yağız Boz', 'Murugavel Ganesan', 'F. Chen', 'B.S. Deepaksubramanyan', 'Brian Bailey']
Semiconductor Engineering
Researchers from A*STAR published a technical paper titled “FAPlace: Joint Optimization of Chiplet Placement and Interposer Footprint for 2.5D Systems.”
Abstract Excerpt: ” We propose FAPlace, a footprint aware mask guided sequential placement framework.
At its core is a novel footprint mask that fuses area compactness with an aspect ratio penalty into a unified spatial cost map.
Experimental results demonstrate that FAPlace reduces wirelength and footprint area while achieving near-unity aspect ratios, without compromising on thermal performance.”
“FAPlace: Joint Optimization of Chiplet Placement and Interposer Footprint for 2.5 D Systems.”