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How To Scale AI Arithmetic Efficiently
['Thomas Ferrere', 'Technical Paper Link', 'Tom Katsioulas', 'Alex', 'Matt Bailey', 'Alexis R. Ware', 'Yağız Boz', 'Murugavel Ganesan', 'F. Chen', 'B.S. Deepaksubramanyan']
Semiconductor Engineering
AI workloads feature matrix multiplications in a variety of number formats, such as INT8, FP4, FP8, FP16 and BF16.
Imagination presents a novel approach to scaling arithmetic performance across number formats.
The multiprecision dot product unit featured in the new E-Series GPUs accelerates matrix multiplications in all the above number formats.
It would lead to matrix multiplication accelerators requiring an ever-growing list of dot product hardware operators, increasing the circuit area beyond the available silicon die.
It works by repurposing the multiplication and summation hardware present in an INT8 dot product to implement an efficient FP8 dot product.