the type of SIMD instruction set architecture that is most common in contemporary consumer grade CPU:s. More specifically, I refer to non-predicated packed SIMD ISA:s where the details of packed SIMD processing is exposed to the software environment. VMX and VelocityEngine)MIPS: MDMX, MIPS-3D, MSA, DSPSPARC: VISAlpha: MVI1 AVX and later x86 SIMD ISA:s (especially AVX-512) incorporate features from vector processing, making them packed SIMD / vector processing hybrids (thus some of the aspects discussed in this article do not fully apply). a SIMD register contains four 32-bit elements), 4*24=96 elements can be processed in the main SIMD loop, and 99-96=3 elements need to be processed after the main loop. For instance if the array length is less than the SIMD register width, the main SIMD loop should be skipped. The key players here are the VEC and LOOP instructions that turn the scalar loop into a vector loop.