The post describes working x86 implementations with 16 and 32 Advanced Matrix Extension (AMX) tile registers, compared with eight tiles on Intel’s shipping AMX implementations. There are no public sources connecting Rosaic to that mystery x86 implementation. Then on July 27, 2026 Ludloff posted again, this time the subject was an x86 implementation with more than the normal eight AMX tiles. The proposed AMX implementation uses EVEX encodings to address TMM0 through TMM31 and doubles TILECFG from 64 to 128 bytes so it can describe the extra registers. AMD and Intel developed ACE through the x86 Ecosystem Advisory Group as a common matrix-acceleration target for future x86 CPUs.