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Pre-Silicon Power Side-Channel Leakage In Processors (University of Lübeck)
['Technical Paper Link', 'Tom Katsioulas', 'Alex', 'Matt Bailey', 'Alexis R. Ware', 'Yağız Boz', 'Murugavel Ganesan', 'F. Chen', 'B.S. Deepaksubramanyan', 'Brian Bailey']
Semiconductor Engineering
Researchers from University of Lübeck published a technical paper titled “SPARC: Automated Root-Cause Analysis of Pre-Silicon Power Side-Channel Leakage in the Processor Design Flow.”
Abstract Excerpt: “This paper presents SPARC, an automated framework for pre-silicon PSCL evaluation and root-cause analysis.
By isolating this activity, SPARC applies statistical leakage tests to detect PSCL, while simultaneously attributing the leakage to specific hardware signals and mapping those signals to the corresponding software instructions. ”
Find the technical paper here.
“SPARC: Automated Root-Cause Analysis of Pre-Silicon Power Side-Channel Leakage in the Processor Design Flow.”