1: IP for multi-die test, including embedded memory test, support for IEEE 1838 DFT, and high-speed access and test for intra-die logic test. Any changes on the design side need to be reflected in updates to the design for test plan, which has become increasingly complicated. This is why ChipAgents focuses on agent-driven static connectivity reasoning, then recommends minimal dynamic tests. Leverage scalable, static verification tools that can handle extremely large, complex designs with billions of connections, going beyond the limits of traditional simulation and formal verification tools. “Using static tools can help catch DFT connectivity issues early at the RTL stage,” Singh added.