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Heterogeneous Multicore System IP
['Nayan Gaywala', 'Technical Paper Link', 'Sf Fiber Techs', 'Mikko Utriainen', 'Raymond Doerr', 'Hoyong Lee', 'Js Paek', 'Larry K', 'Linda Christensen', 'David Muncier']
Semiconductor Engineering
A heterogeneous multicore system enables designers to reduce energy and area costs while meeting performance requirements across various workloads.
This blog presents a heterogeneous multicore system built with the RISC-V Host CPU and Cadence IP: Xtensa DSPs, and the Janus Network-on-Chip (NoC).
System memory bandwidth and capacity are another challenge when building a heterogeneous system with multiple compute units.
Customers can easily build a SystemC model of their heterogeneous multicore system using these components.
SummaryAs shown, customers can easily design, validate, and debug a heterogeneous multicore system using Cadence IP and tools, even when combined with other IP.