Hierarchical device planning directly addresses this by integrating established hierarchical design methodology techniques into the realm of advanced IC packaging and, as such, enables more robust and flexible STCO. Hierarchical device planning directly addresses this by integrating established hierarchical design methodology techniques—long characteristic of chip design—into the realm of advanced IC packaging. 3: Connectivity in a hierarchical IC package floorplan, showing that bumps within the sub-devices are represented at the top level. With hierarchical device planning, designers can simply modify the relevant parameters of a region, and the system automatically updates the circuit. For more in depth look at these two technologies, please read the new paper from Siemens, Hierarchical device planning: Navigating 3D IC intricacies with STCO.